A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems
A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems
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DOI：
10.1109/tcsi.2007.900179
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发表时间：
2007-07-01
影响因子：
5.1
通讯作者：
Linares-Barranco, Bernabe
中科院分区：
文献类型：
--
作者：
Costas-Santos, Jesus;Serrano-Gotarredona, Teresa;Linares-Barranco, Bernabe
我们提出了一个32 x 32像素对比度视网膜微芯片，提供其输出作为地址事件表示（AER）流。空间对比度计算为像素光电流与通过扩散网络获得的相邻像素之间的局部平均值之比。这种基于电流的计算在相邻像素之间产生了大量的不匹配，因为电流可以低到几皮安培。因此，一个紧凑的校准电路已包括修剪每个像素。测量显示失配标准偏差从57%减少到6.6%（室内光）。本文介绍了像素的设计及其空间对比度计算和标定部分。大约三分之一的像素面积用于5位校准电路。像素面积为58 μ m × 56 μ m，在1 khz事件速率下，其电流消耗约为20 nA。在标准的0.35 μ m CMOS工艺中，提供了广泛的实验结果。
We present a 32 x 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring,pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 mu m x 56 mu m, while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35-mu m CMOS process.