An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder
An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder
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DOI：
10.4218/etrij.05.0905.0032
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发表时间：
2005-10
期刊：
影响因子：
1.4
通讯作者：
Kibum Suh;Seongmo Park;Hanjin Cho
中科院分区：
文献类型：
--
作者：
Kibum Suh;Seongmo Park;Hanjin Cho
在本文中，我们提出了一种新的硬件架构的帧内预测，整数变换，量化，逆整数变换，逆量化和模式决策模块的宏块引擎的一个新的视频编码标准，H. 264。为了减少H.264帧内预测、变换/量化、逆量化/逆变换的周期，提出了一种I16 MB模式下的周期开销减少方法。该方法在16×16的预测过程中，通过4×4的Hadamard变换和量化，对所有宏块类型的情况下，一个宏块可以处理927个周期。该模块采用Verilog硬件描述语言（HDL）设计，采用Hynix 0.35 µm TLM（三层金属）库，在54 MHz时钟下工作。
In this paper, we propose a novel hardware architecture for an intra‐prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing 4×4 Hadamard transform and quantization during 16×16 prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix 0.35 µm TLM (triple layer metal) library.