Design and CAD methodologies for low power gate-level monolithic 3D ICs
Design and CAD methodologies for low power gate-level monolithic 3D ICs
复制标题
低功耗门级单片 3D IC 的设计和 CAD 方法
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
S. Lim
中科院分区：
文献类型：
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作者：
Shreepad Panth;K. Samadi;Yang Du;S. Lim
在栅极级的整体3D IC（M3D）中，单个逻辑门中的所有晶体管均占据相同的层，并且不同层中的门是使用纳米尺度整体上层层间vias连接的。这种设计样式具有平坦实施（与块级M3D不同）提供的优质功率性能质量，而零总硅面积为零2D（与晶体管级M3D不同）。在本文中，我们首次开发了Gate级M3D的完整的RTL到GDSII设计流。我们的工具流基于为2D IC构建的商业工具，并通过我们的3D特定方法来增强。我们将这种流程与28nm PDK一起为OpenSparc T2核心构建布局。我们的模拟表明，与商业质量2D IC设计相比，在相同的性能下，Gate级M3D提供了16％的总功率，而面积为0％。
In a gate-level monolithic 3D IC (M3D), all the transistors in a single logic gate occupy the same tier, and gates in different tiers are connected using nano-scale monolithic inter-tier vias. This design style has the benefit of the superior power-performance quality offered by flat implementations (unlike block-level M3D), and zero total silicon area overhead compared to 2D (unlike transistor-level M3D). In this paper we develop, for the first time, a complete RTL-to-GDSII design flow for gate-level M3D. Our tool flow is based on commercial tools built for 2D ICs and enhanced with our 3D-specific methodologies. We use this flow along with a 28nm PDK to build layouts for the OpenSPARC T2 core. Our simulations show that at the same performance, gate-level M3D offers 16% total power reduction with 0% area overhead compared to commercial quality 2D IC designs.