A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard
A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard
复制标题
支持 VVC 标准混合块大小的流水线 2D 转换架构
DOI：
10.1109/tcsvt.2019.2934752
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发表时间：
2020-09-01
影响因子：
8.4
通讯作者：
Zeng, Xiaoyang
中科院分区：
文献类型：
--
作者：
Fan, Yibo;Zeng, Yixuan;Zeng, Xiaoyang
对于下一代视频编码标准通用视频编码（VVC），提出了几个新的贡献来提高编码效率，特别是在变换操作方面。本文为VVC标准提出了一种统一的$32\ × 32$基于块的变换体系结构，该体系结构支持各种尺寸的2D离散正弦变换- vii （DST-VII）和离散余弦变换- viii （DCT-VIII）。主要有三个贡献：1)采用n维降法加法图（ragn）算法设计最小的面向加法器的计算单元。2)非对称变换单元的存储可以在基于双端口sram的转置存储器中实现。3)实现了混合块大小的流水线二维变换，每周期的吞吐率为32个样本。综合结果表明，该建筑与其他先进建筑相比，面积可减少73.1%。此外，可实现4.9%至9.9%的节电。对于转置存储器，使用SRAM可以节省至少21.9%的面积。
For the next-generation video coding standard Versatile Video Coding (VVC), several new contributions have been proposed to improve the coding efficiency, especially in the transformation operations. This paper proposes a unified $32\times 32$ block-based transform architecture for the VVC standard that enables 2D Discrete Sine Transform-VII (DST-VII) and Discrete Cosine Transform-VIII (DCT-VIII) of all sizes. It mainly gives three contributions: 1) The N-Dimensional Reduced Adder Graph (RAG-n) algorithm is adopted to design the minimal adder-oriented computational units. 2) The storage of the asymmetric transform units can be realized in the dual-port SRAM-based transpose memory. 3) The pipelined 2D transformations of mixed block sizes are achieved with the throughput rate of 32 samples per cycle. The synthesis results indicate that this architecture can reduce area by up to 73.1% compared with other state-of-the-art works. Moreover, power saving ranging from 4.9% to 9.9% can be achieved. Regarding the transpose memory, at least 21.9% of the area can be saved by using SRAM.