A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures
A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures
复制标题
分布式寄存器架构的过程变化感知多场景高级综合算法
DOI：
10.1109/socc.2015.7406898
复制
发表时间：
2015
期刊：
影响因子：
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通讯作者：
N. Togawa
中科院分区：
文献类型：
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作者：
Koki Igawa;Youhua Shi;M. Yanagisawa;N. Togawa
为了解决过程变化问题，我们可以定义几个场景，每个场景对应于特定的LSI行为，例如典型场景和最坏场景。通过设计同时实现多个场景的单个LSI芯片，我们可以拥有工艺变化容限LSI芯片。在本文中，我们提出了一个工艺变化感知的低延迟和多场景的高层次综合算法针对新的分布式寄存器架构，称为HDR架构。我们假设两个场景，一个典型的情况下，一个最坏的情况下，并实现到一个单一的芯片。我们首先独立地调度/绑定每个场景。之后，我们共同的调度/绑定结果的典型情况下和最坏的情况下，从而产生一个共同的面积最小化的布局结果。实验结果表明，我们的算法减少了延迟的典型情况下的场景高达50%，而不增加延迟的最坏情况下，与现有的几种方法相比。
In order to tackle a process-variation problem, we can define several scenarios, each of which corresponds to a particular LSI behavior, such as a typical-case scenario and a worst-case scenario. By designing a single LSI chip which realizes multiple scenarios simultaneously, we can have a process-variation-tolerant LSI chip. In this paper, we propose a process-variation-aware low-latency and multi-scenario high-level synthesis algorithm targeting new distributed-register architectures, called HDR architectures. We assume two scenarios, a typical-case scenario and a worst-case scenario, and realize them onto a single chip. We first schedule/bind each of the scenarios independently. After that, we commonize the scheduling/binding results for the typical-case and worst-case scenarios and thus generate a commonized area-minimized floorplan result. Experimental results show that our algorithm reduces the latency of the typical-case scenario by up to 50% without increasing the latency of the worst-case scenario, compared with several existing methods.