Guiding gate-etch process development using 3D surface reaction modeling for 7nm and beyond
Guiding gate-etch process development using 3D surface reaction modeling for 7nm and beyond
复制标题
使用 7nm 及以上 3D 表面反应建模指导栅极蚀刻工艺开发
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
A. Ranjan
中科院分区：
文献类型：
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作者：
D. Dunn;J. Sporre;V. Deshpande;M. Oulmane;R. Gull;P. Ventzek;A. Ranjan
越来越多的先进工艺节点，如7nm （N7）基本上是3D的，需要严格控制高纵横比特征的关键尺寸。这些节点的工艺集成需要对复杂的物理机制有深刻的理解，以控制从光刻到最终蚀刻的关键尺寸。多晶硅栅极蚀刻工艺是高级节点的几种器件架构中的关键步骤，这些节点依赖于自对齐模式方法来定义栅极。这些工艺需要满足几个关键指标：(a)高纵横比的垂直蚀刻轮廓；(b)清洁闸门侧壁，无蚀刻过程残留物；(c)保护关键建筑元素（如鳍）的氧化膜的侵蚀最小；(e)与关键器件元件栅极接口处无残留角。在这项研究中，我们探索了如何使用混合建模方法来模拟多步finFET多晶硅栅极蚀刻过程。通过硬掩码组装的图形化过程的初始部分使用过程仿真建模。栅极定义的重要方面，然后使用粒子蒙特卡罗（PMC）特征比例模型，其中包含表面化学反应必要时，从蚀刻室的模拟中导出PMC模型的物质和能量通量输入。建模的多晶硅栅极蚀刻过程包括几个步骤，包括硬掩膜突破步骤（BT），主要特征蚀刻步骤（ME）和控制栅极鳍界面栅极轮廓的过蚀刻步骤（OE）。这种蚀刻流的另一个限制是，在最后的轮廓调整步骤后，翅片间隔氧化物保持完整。从这些过程中需要的自然优化是最大化垂直闸门轮廓，同时最小化翅片间隔膜的侵蚀
Increasingly, advanced process nodes such as 7nm (N7) are fundamentally 3D and require stringent control of critical dimensions over high aspect ratio features. Process integration in these nodes requires a deep understanding of complex physical mechanisms to control critical dimensions from lithography through final etch. Polysilicon gate etch processes are critical steps in several device architectures for advanced nodes that rely on self-aligned patterning approaches to gate definition. These processes are required to meet several key metrics: (a) vertical etch profiles over high aspect ratios; (b) clean gate sidewalls free of etch process residue; (c) minimal erosion of liner oxide films protecting key architectural elements such as fins; and (e) residue free corners at gate interfaces with critical device elements. In this study, we explore how hybrid modeling approaches can be used to model a multi-step finFET polysilicon gate etch process. Initial parts of the patterning process through hardmask assembly are modeled using process emulation. Important aspects of gate definition are then modeled using a particle Monte Carlo (PMC) feature scale model that incorporates surface chemical reactions.1 When necessary, species and energy flux inputs to the PMC model are derived from simulations of the etch chamber. The modeled polysilicon gate etch process consists of several steps including a hard mask breakthrough step (BT), main feature etch steps (ME), and over-etch steps (OE) that control gate profiles at the gate fin interface. An additional constraint on this etch flow is that fin spacer oxides are left intact after final profile tuning steps. A natural optimization required from these processes is to maximize vertical gate profiles while minimizing erosion of fin spacer films.2