Side Channel Power Analysis Resistance Evaluation of Masked Adders on FPGA
Side Channel Power Analysis Resistance Evaluation of Masked Adders on FPGA
复制标题
FPGA 上屏蔽加法器的侧通道功率分析电阻评估
DOI：
10.11591/ijres.v12.i1.pp97-112
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发表时间：
2023
期刊：
影响因子：
--
通讯作者：
Hiroyuki Tomiyama
中科院分区：
文献类型：
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作者：
Yilin Zhao;Hiroki Nishikawa;Xiangbo Kong;Hiroyuki Tomiyama
由于许多物联网（IoT）设备受到侧信道攻击的威胁，因此安全措施对于其安全使用至关重要。然而，物联网设备种类繁多，因此所需的准确性取决于系统的应用。此外，近年来与算术运算相关的安全性也受到了人们的关注。因此，本文提出了现场可编程门阵列（fpga）上加法器掩码的经验实验，并通过改变掩码的位长度来探索成本和安全性之间的权衡。实验结果表明，掩码提高了功率分析的抗攻击能力，增加用于掩码的随机数的位长可以提高安全性。特别是串联的掩码加法器，可以有效地提高功率分析的抗攻击能力。
Since many internet of things (IoT) devices are threatened by side-channel attacks, security measures are essential for their safe use. However, there are a variety of IoT devices, so the accuracy required depends on the system’s application. In addition, security related to arithmetic operations has been attracting attention in recent years. Therefore, this paper presents an empirical experiment of masking for adders on field programmable gate arrays (FPGAs) and explores the trade-off between cost and security by varying the bit length of the mask. The experimental results show that masking improves power analysis attack resistance, and increasing the bit length of the random numbers used for masking increases security. In particular, the series-connected masked adder is found to be effective in improving power analysis attack resistance.