Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing margins
Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing margins
复制标题
使用遗传算法对数字 LSI 进行制造后时钟时序调整，确保时序裕度
DOI：
10.1109/icsmc.2004.1400913
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发表时间：
2004
期刊：
影响因子：
--
通讯作者：
T. Higuchi
中科院分区：
文献类型：
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作者：
M. Murakawa;E. Takahashi;T. Susa;T. Higuchi
为了解决数字大规模集成电路中时钟时序波动的问题(也称为时钟偏差问题)，提出了一种基于遗传算法(GA)的时钟调整方法，该方法确保了时钟时序的健壮性，以应对LSI环境中的温度或电源电压等波动。该方法通过专用可调电路和GA调整软件相结合来实现，插入时钟线的多个可调延迟电路的值由GA软件在制造后确定。仿真结果表明，该方法可以在保证足够的时序裕度的前提下，将已开发测试芯片的运算率提高97%(最大)。
To solve the problem of fluctuations in clock timing with digital LSI (also known as the "clock skew" problem), we propose a genetic algorithm (GA) based clock adjustment method that ensures robust clock timing to cope with fluctuations in the LSI environment such as temperature or power supply voltage. This method is realized by the combination of dedicated adjustable circuitry and adjustment GA software, with the values for multiple adjustable delay circuits inserted into the clock lines being determined by the GA software after fabrication. Simulation results show that proposed method can enhance the operational yields of developed test chips by 97% (maximum) while ensuring sufficient timing margins.