Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicide CMOS technology
Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicide CMOS technology
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DOI：
10.1109/vtsa.2001.934478
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
M. Ker;Kei-Kang Hong;Tung-Yang Chen;H. Tang;S. Huang;S.-S. Chen-S.;C. Huang;M. Wang;Y. Loh
中科院分区：
文献类型：
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作者：
M. Ker;Kei-Kang Hong;Tung-Yang Chen;H. Tang;S. Huang;S.-S. Chen-S.;C. Huang;M. Wang;Y. Loh
采用0.15-/spl μ m部分耗尽绝缘体上硅（SOI）盐化CMOS工艺制备了四种不同布局结构的CMOS器件，通过ESD测试仪验证了器件的静电放电（ESD）稳健性。利用传输线脉冲发生器（TLPG）测量了CMOS器件的二次击穿电流（It2）。为了找到片上ESD保护设计的最佳布局规则，研究了SOI CMOS工艺中ESD鲁棒性与CMOS器件布局参数的关系。在此SOI CMOS工艺中，还比较了采用门驱动和衬底触发技术设计的ESD箝位电路的有效性。
Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-/spl mu/m partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by an ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.