Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch
Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch
复制标题
通过可编程路由开关和可编程电源开关过驱动实现 CAAC-IGZO FPGA 的亚阈值操作
DOI：
10.1109/tvlsi.2016.2571744
复制
发表时间：
2017
影响因子：
2.8
通讯作者：
S. Yamazaki
中科院分区：
文献类型：
--
作者：
M. Kozuma;Y. Okamoto;T. Nakagawa;T. Aoki;Y. Kurokawa;T. Ikeda;Y. Ieda;Naoto Yamade;H. Miyairi;M. Ikeda;M. Fujita;S. Yamazaki
已经开发了使用c轴对准晶体铟镓锌氧化物（CAAC-IGZO）的晶体氧化物半导体的现场可编程门阵列（FPGA），其能够用于能量收集的亚阈值操作。为了实现亚阈值操作，CAAC-IGZO FPGA具有被设计为使用CAAC-IGZO FET的升压通过门的扩展的结构，并且采用可编程路由开关和用于功率门控（PG）的可编程功率开关的过驱动。CAAC-IGZO FET用于提供具有优异电荷保持的理想浮置栅极。采用0.8 μ mCAAC-IGZO/0.18 μ mCMOS混合工艺制造的芯片实现了亚阈值操作，同时保持了我们以前研究中提出的常关计算所需的功能。具体而言，这些特征通过用于各个可编程逻辑元件（PLEs）的细粒度PG、上下文之间的快速配置切换以及PLEs中的易失性寄存器和非易失性影子寄存器之间的加载/存储来实现。芯片工作在最低工作电压为180 mV的组合电路配置证明。该芯片采用时序电路配置，工作电压最低为190 mV，频率为12.5 kHz，330 mV时的最小功耗延迟积为3.40 pJ/操作。
A field-programmable gate array (FPGA) using a crystalline oxide semiconductor of c-axis-aligned crystal indium-gallium-zinc oxide (CAAC-IGZO) has been developed, which is capable of subthreshold operation used for energy harvesting. To achieve subthreshold operation, the CAAC-IGZO FPGA has a structure designed as an extension of a boosting pass gate using a CAAC-IGZO FET and employs overdriving of a programmable routing switch and a programmable power switch for power gating (PG). A CAAC-IGZO FET is used to give an ideal floating gate with excellent charge retention. A chip fabricated using a 0.8-μm CAAC-IGZO/0.18-μm CMOS hybrid process achieves subthreshold operation while maintaining the features required for normally off computing proposed in our previous study. Specifically, these features are realized by fine-grained PG for individual programmable logic elements (PLEs), fast configuration switching between contexts, and load/store between a volatile register and a nonvolatile shadow register in the PLEs. The chip operation at a minimum operating voltage of 180 mV with a combinational circuit configuration is demonstrated. With a sequential circuit configuration, the chip operates at a minimum operating voltage of 190 mV with 12.5 kHz, and the minimum power-delay product is 3.40 pJ/operation at 330 mV.