CoW Package Solution for Improving Thermal Characteristic of TSV-SiP for AI-Inference

CoW Package Solution for Improving Thermal Characteristic of TSV-SiP for AI-Inference
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用于改善 AI 推理 TSV-SiP 热特性的 CoW 封装解决方案

DOI:
10.1109/ectc32696.2021.00182
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发表时间:
2021
期刊:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC)
影响因子:
--
通讯作者:
Hyoeun Kim
Hyoeun Kim
中科院分区:
--
文献类型:
--
作者:
S. Seo;Chajea Jo;Mina Choi;Taehwan Kim;Hyoeun Kim

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用于人工智能推理的逻辑器件需要高带宽和低延迟特性以提高响应速度。为了克服单个逻辑芯片的尺寸限制并确保这些特性,不可避免地要将SRAM功能分离以增加存储器容量,并应用直接与逻辑堆叠的3D封装结构。堆叠逻辑和存储器的结构可以在四种情况下实现;面对面和背面(B2 F),SRAM上的逻辑和SRAM逻辑。其中,在具有B2 F的SRAM on Logic中的热特性并不比其他结构更强,因为在大部分热量通过安装在封装顶部的冷却器强制排出的服务器环境中,从逻辑前侧产生的大量热量并不直接通过Si单独到达冷却器,而是通过微凸块接合层和整个SRAM芯片。本研究提出了一种降低微凸块结热阻的详细方法,以改善逻辑堆栈封装结构上的静态随机存取存储器的热特性。测试车辆包括顶部芯片(93平方毫米)和底部芯片(103平方毫米)与微凸块连接的40 μ m $以下的间距和20 μ m $以下的直径。从接头结构、材料、版图设计等方面分析了影响封装热阻的主要因素,并在实现实际封装后进行了热阻测量和比较,以准确确定各主要因素对降低封装热阻的影响。
Logic device for AI-inference needs high band width and low latency characteristics to increase the response speed. In order to overcome the size limitation of a single logic chip and secure these characteristics, it is inevitable to separate the SRAM function to increase the memory capacity and apply a 3D package structure that directly stacks with logic. The structure of stacking logic and memory can be implemented in four cases; face to face and back to face (B2F), Logic on SRAM and SRAM on Logic. Among them, thermal characteristics in SRAM on Logic with B2F are not stronger than other structures because in a server environment where most of the heat is forcibly discharged through the cooler installed on the top of package, a lot of heat generated from the logic front side does not go directly to the cooler through Si alone, but passes through the micro-bump bonding layer and the entire SRAM chip. In this study, it was presented that a detailed method for reducing the thermal resistance of the micro-bump junction in order to improve the thermal characteristics in the SRAM on Logic stack package structure. Test vehicle consisted of top chip (93mm2) and bottom chip (103mm2) with micro-bump connections of under $40 \mu\mathrm{m}$ in pitch and under $20 \mu\mathrm{m}$ in diameter. The main influence factors were analyzed in terms of the joint structure, material, and layout design, and thermal resistance was measured and compared after achieving actual package to confirm exactly the effect of each major factor on reducing package thermal resistance.