A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
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DOI：
10.1109/jssc.2007.908692
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发表时间：
2007-11
影响因子：
5.4
通讯作者：
J. Poulton;R. Palmer;Andrew M. Fuller;T. Greer;J. Eyles;W. Dally;M. Horowitz
中科院分区：
文献类型：
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作者：
J. Poulton;R. Palmer;Andrew M. Fuller;T. Greer;J. Eyles;W. Dally;M. Horowitz
本文介绍了一种6.25 Gb/s的14 mW收发器在90 nm CMOS芯片到芯片的应用。该收发器采用了许多降低功耗的特性，包括共享LC-PLL时钟乘法器、电感负载谐振时钟分配网络、低摆幅和可编程电压模式发射器、接收器内的软件控制时钟和数据恢复（CDR）和自适应均衡，以及用于CDR的新型PLL相位旋转器。该设计可以在误码率为10-15或更低的情况下以-15 dB或更大的信道衰减工作，同时每个收发器的功耗小于2.25 mW/Gb/s。
This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.