A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices
A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices
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适用于 Tiny-Al 边缘设备的 40 nm、2M 单元、8b 精度、混合 SLC-MLC PCM 内存计算宏，具有 20.5 - 65.0TOPS/W
DOI：
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发表时间：
2022
期刊：
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通讯作者：
M. Chang
中科院分区：
文献类型：
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作者：
W. Khwa;Yen;Chuan;Sheng;Chun;Tai;Fu;Shao;T. Lee;M. Chang
具有足够大的片上存储容量的高效边缘计算在万物互联时代至关重要。非易失性内存计算（nvCIM）通过使计算更接近内存来减少数据传输开销[1]-[4]。而多层存储单元（MLC）比单层存储单元（SLC）具有更高的存储密度。已经提出了一些MLC或模拟nvCIM设计，但它们要么针对更简单的神经网络模型[5]，要么使用面积效率较低的差分单元[6]来实现。此外，使用一种存储类型来表示整个权重向量不会利用高位和低位之间的巨大准确性差异。
Efficient edge computing, with sufficiently large on-chip memory capacity, is essential in the internet-of-everything era. Nonvolatile computing-in-memory (nvCIM) reduces the data transfer overhead by bringing computation closer, in proximity, to the memory [1]–[4]. While the multi-level cell (MLC) has higher storage density than the single-level cell (SLC). A few MLC or analog nvCIM designs had been proposed, but they either target simpler neural-net models [5] or are implemented using a less area-efficient differential cell [6]. Furthermore, representing the entire weight vector using one storage type does not exploit the drastic accuracy difference between the upper and the lower bits.