Improving FPGA Reliability with Wear-Levelling
Improving FPGA Reliability with Wear-Levelling
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DOI：
10.1109/fpl.2011.65
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发表时间：
2011-09
期刊：
影响因子：
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通讯作者：
Edward A. Stott;P. Cheung
中科院分区：
文献类型：
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作者：
Edward A. Stott;P. Cheung
随着 VLSI 电路的几何尺寸越来越小，可靠性正成为一个日益严重的问题。 FPGA 的灵活性使新技术能够应对这一挑战，其中一项技术就是磨损均衡：定期重新配置以消除电应力热点。在这项工作中，我们在 FPGA 中进行了加速寿命实验，以评估三种磨损均衡策略减少时序退化的可行性。与静态配置相比，这三种技术都显着提高了鲁棒性，并且我们已经证明磨损均衡是一种很有前景的提高 FPGA 可靠性的工具。
As VLSI circuits achieve smaller geometries, reliability is becoming an growing problem. The flexibility of FPGAs enables novel techniques for meeting this challenge, and one such technique is wear-levelling: periodic reconfiguration to eliminate electrical stress hotspots. In this work we have have carried out accelerated-life experiments in FPGAs to assess the feasibility of three wear-levelling strategies for reducing timing degradation. All three techniques resulted in significant improvements to robustness compared with a static configuration, and we have demonstrated that wear-levelling is a promising tool for improving FPGA reliability.