Process variation in embedded memories: failure analysis and variation aware architecture
Process variation in embedded memories: failure analysis and variation aware architecture
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DOI：
10.1109/jssc.2005.852159
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发表时间：
2005-08
影响因子：
5.4
通讯作者：
A. Agarwal;B. Paul;S. Mukhopadhyay;K. Roy
中科院分区：
文献类型：
--
作者：
A. Agarwal;B. Paul;S. Mukhopadhyay;K. Roy
随着器件尺寸的缩小，器件沟道区掺杂原子数量和位置的微观变化导致器件特性（如阈值电压）出现越来越受限的电学偏差。这些原子级的本征涨落无法通过制造工艺的外部控制消除，并且在面积受限的电路（如静态随机存取存储器单元）中常用的最小几何尺寸晶体管中最为显著。因此，在亚50纳米技术中，由于工艺变化，预计存储器中的大量单元会出现故障。本文分析了工艺变化下的静态随机存取存储器单元故障，并提出了适用于高性能应用的新型感知变化的缓存架构。所提出的架构自适应地调整缓存大小以避开故障单元，从而提高成品率。该方案对处理器架构是透明的，并且能量和面积开销可忽略不计。在一个32K直接映射一级缓存上的实验结果表明，与原始的33%相比，所提出的架构可实现93%的成品率。SimpleScalar模拟显示，对于我们所提出的方案可容忍最大数量故障单元的芯片，使用所提出的架构设计数据缓存和指令缓存分别导致1.5%和5.7%的平均CPU性能损失（基于SPEC 2000基准测试）。
With scaling of device dimensions, microscopic variations in number and location of dopant atoms in the channel region of the device induce increasingly limiting electrical deviations in device characteristics such as threshold voltage. These atomic-level intrinsic fluctuations cannot be eliminated by external control of the manufacturing process and are most pronounced in minimum-geometry transistors commonly used in area-constrained circuits such as SRAM cells. Consequently, a large number of cells in a memory are expected to be faulty due to process variations in sub-50-nm technologies. This paper analyzes SRAM cell failures under process variation and proposes new variation-aware cache architecture suitable for high performance applications. The proposed architecture adaptively resizes the cache to avoid faulty cells, thereby improving yield. This scheme is transparent to processor architecture and has negligible energy and area overhead. Experimental results on a 32 K direct map L1 cache show that the proposed architecture can achieve 93% yield compared to its original 33%. The Simplescalar simulation shows that designing the data and instruction cache using the proposed architecture results in 1.5% and 5.7% average CPU performance loss (over SPEC 2000 benchmarks), respectively, for the chips with maximum number of faulty cells which can be tolerated by our proposed scheme.