Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors
Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors
复制标题
内存映射 SPM：保护嵌入式系统中的指令暂存器内存免受软错误的影响
DOI：
10.1109/edcc.2012.13
复制
发表时间：
2012
期刊：
影响因子：
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通讯作者：
S. Miremadi
中科院分区：
文献类型：
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作者：
Hamed Farbeh;M. Fazeli;Faramarz Khosravi;S. Miremadi
可预测性、能耗、面积和可靠性是嵌入式系统的主要关注点。使用刮板存储器（spm）代替缓存存储器在满足这些问题方面发挥着越来越重要的作用。缓存和SPM作为片上SRAM存储器都极易受到软错误的影响，因为它们包含了最常用的程序块，它们的错误很容易在系统中传播，导致错误的结果。与指令缓存不同，指令SPM中的错误不能仅使用奇偶校验位通过使错误行无效来纠正。本研究提出一种低成本的机制来保护指令SPM免受软错误的影响。背后的主要思想提出的机制包括四个阶段:1)使用奇偶校验码错误检测的SPM, 2)保持一个地址匹配表主内存中存储的地址复制的SPM块内存,在动态SPM, 3)分配一个特定的段的主要内存作为SPM备份,在静态SPM和4)从错误中恢复使用一个中断服务例程(ISR)。与单错误纠错/双错误检测（SEC-DED）方案相比，通过使用2位交错奇偶校验每字，所提出的机制可以纠正至少3位错误，而SEC-DED只能纠正单位错误和检测2位错误。实验结果表明，对于4Kbyte的SPM，该机制的能量消耗和面积开销分别比SEC-DED减少约22%和15%。此外，与SEC-DED相比，该机制的性能损失降低了10倍。
Predictability, energy consumption, area and reliability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories play an increasing role to satisfy these concerns. Both cache and SPM as on-chip SRAM memories are highly vulnerable to soft errors and as they contain the most frequently used blocks of the program, their errors can easily propagate in system leading to erroneous results. Unlike the instruction cache, an error in the instruction SPM cannot be corrected using only parity bits by invalidating the erroneous line. This study suggests a low-cost mechanism to protect the instruction SPM against soft errors. The main idea underlying the proposed mechanism includes four stages: 1) to use parity codes for error detection in the SPM, 2) to keep an address matching table in the main memory to store the address of the copy of SPM blocks in the main memory, in the case of dynamic SPM, 3) to allocate a specific segment of the main memory as an SPM backup, in the case of static SPM, and 4) to recover from errors using an interrupt service routine (ISR). Compared with a single error correction /double error detection (SEC-DED) scheme, by using a 2-bit interleaved-parity per word, the proposed mechanism can correct at least three bit errors, while SEC-DED is capable of correcting only single bit error and detecting 2-bit errors. The experimental results reveal that the energy consumption and area overheads of the proposed mechanism are approximately 22% and 15% less than that of SEC-DED for a 4Kbyte SPM, respectively. Moreover, this mechanism provides 10 times lower performance loss compared with SEC-DED.
搜索与 B/R4RGS 结合的支架蛋白
DOI：
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发表时间：
2006
期刊：
影响因子：
--
作者：
藤井 聖司;牟田 貴里子;齊藤 修
通讯作者：
齊藤 修