Encapsulation of graphene transistors and vertical device integration by interface engineering with atomic layer deposited oxide
Encapsulation of graphene transistors and vertical device integration by interface engineering with atomic layer deposited oxide
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DOI：
10.1088/2053-1583/4/1/011008
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发表时间：
2017-03-01
期刊：
影响因子：
5.5
通讯作者：
Hofmann, Stephan
中科院分区：
文献类型：
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作者：
Alexander-Webber, Jack A.;Sagade, Abhay A.;Hofmann, Stephan
我们展示了一种简单的，可扩展的方法来实现封装的石墨烯晶体管与可忽略的栅极滞后，低掺杂水平和增强的迁移率相比，制造的设备。我们通过调整生长参数来设计石墨烯和原子层沉积（ALD）Al2O3之间的界面，以实现有效的器件封装，同时使底层栅极电介质中的电荷陷阱钝化。我们涉及的石墨烯附近的电荷陷阱态的钝化ALD氧化物的共形生长所管辖的原位气态H2O预处理。我们证明了这种封装技术的长期稳定性和由此产生的对额外的光刻步骤的不敏感性，以实现用于多堆叠电子制造的石墨烯的垂直器件集成。
We demonstrate a simple, scalable approach to achieve encapsulated graphene transistors with negligible gate hysteresis, low doping levels and enhanced mobility compared to as-fabricated devices. We engineer the interface between graphene and atomic layer deposited (ALD) Al2O3 by tailoring the growth parameters to achieve effective device encapsulation whilst enabling the passivation of charge traps in the underlying gate dielectric. We relate the passivation of charge trap states in the vicinity of the graphene to conformal growth of ALD oxide governed by in situ gaseous H2O pretreatments. We demonstrate the long term stability of such encapsulation techniques and the resulting insensitivity towards additional lithography steps to enable vertical device integration of graphene for multi-stacked electronics fabrication.