A single channel 6-bit 900MS/s 2-bits per stage asynchronous binary search ADC
A single channel 6-bit 900MS/s 2-bits per stage asynchronous binary search ADC
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DOI：
10.1109/mwscas.2011.6026344
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发表时间：
2011-09
期刊：
影响因子：
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通讯作者：
A. Mesgarani;S. Ay
中科院分区：
文献类型：
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作者：
A. Mesgarani;S. Ay
本文介绍了一种新的单通道6位900 MS/s异步二进制搜索模数转换器。所提出的ADC基于二进制搜索原理工作，如逐次逼近寄存器（SAR）ADC。与SAR ADC相比，采用两种设计技术，速度有了显著提高。通过在开环配置中使用异步时钟生成来实现二进制搜索，SAR ADC的反馈路径中的延迟被显著放宽。此外，在所提出的异步二进制搜索ADC中，在ADC的每一级中解析两位。通过在每一级中解析两位，所提出的ADC的工作速度可以是传统异步二进制搜索ADC的两倍。采用90 nm CMOS工艺设计了单通道6位900 MS/s ADC。仿真结果表明，在1.2V电源电压下，该ADC的SNDR峰值为35.82dB，功耗为4.33mW。它达到了95.3fJ/转换码FoM。
This paper presents a new single channel 6-bit 900MS/s asynchronous binary search analog to digital converter (ADC). The proposed ADC works based on binary search principle like the Successive Approximation Register (SAR) ADC. Compared to SAR ADC the speed is improved significantly adopting two design techniques. By implementing the binary search in an open loop configuration using asynchronous clock generation the delay in the feedback path of the SAR ADC is relaxed significantly. Moreover in the proposed asynchronous binary search ADC two bits are resolved in each stage of the ADC. By resolving two bits in each stage the proposed ADC can operate twice as fast as conventional asynchronous binary search ADCs. The proposed single channel 6-bit 900MS/s ADC was designed in 90nm CMOS process. Simulation results show that the proposed ADC reaches a peak SNDR of 35.82dB consuming 4.33mW from a single 1.2V power supply. It achieves of 95.3fJ/conv.code FoM.