Asymmetric transistor sizing targeting radiation-hardened circuits
Asymmetric transistor sizing targeting radiation-hardened circuits
复制标题
针对抗辐射电路的不对称晶体管尺寸调整
DOI：
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复制
发表时间：
2012
期刊：
影响因子：
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通讯作者：
R. Reis
中科院分区：
文献类型：
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作者：
C. Lazzari;G. Wirth;F. Kastensmidt;L. Anghel;R. Reis
本文提出了一种技术，以提高电路的可靠性在高能粒子辐照下的最关键的路径中的晶体管。首先，分析映射电路的SET脆弱性，以确定最敏感的节点。电路的灵敏度由逻辑和电气屏蔽定义。一旦选择了最关键的节点，晶体管尺寸调整算法就能够单独调整上拉和下拉晶体管的尺寸。与门尺寸调整和门复制技术相比，非对称双金属栅提供了有趣的面积和性能权衡。结果表明，非常小的面积和性能的处罚电路工作在地面水平的130纳米技术工艺。
This article proposes a technique to improve the dependability of circuits under energetic particle irradiation by resizing transistors in the most critical paths. First, the SET vulnerability of a mapped circuit is analyzed to identify the most sensitive nodes. The sensitivity of the circuit is defined by the logical and electrical masking. Once the most critical nodes are selected, a transistor sizing algorithm is able to resize the pull-up and pull-down transistors separately. The asymmetric resizing offers interesting area and performance trade-off in comparison with gate sizing and gate duplication techniques. Results show very small area and performance penalties for circuits operating at ground level for a 130-nm technology process.