A 265- $mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS
A 265- $mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS
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采用 65 nm CMOS 封装、具有无缝自动切换子采样/采样反馈路径和占空比锁频环的 265-$mu$W 小数-${N}$ 数字 PLL
DOI：
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发表时间：
2019
影响因子：
5.4
通讯作者：
T. Someya
中科院分区：
文献类型：
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作者：
Hanli Liu;A. Shirane;K. Okada;Zheng Sun;Hongye Huang;W. Deng;T. Siriburanon;Jian Pang;Yun Wang;Rui Wu;T. Someya
本文提出了一种小数 N 数字锁相环 (DPLL)，可实现 265-<inline-formula> <tex-math notation="LaTeX">$mu ext{W}$ </tex-math></inline-formula> 超低功耗操作。所提出的开关反馈可以将DPLL从采样操作无缝地改变为子采样操作，而不干扰DPLL的锁相状态，从而减少在振荡器频率下工作的构建块的数量，从而显着降低功耗。随着高频电路数量的减少，充分利用参考频率的缩放来降低DPLL的功耗。与死区外检测器和后台运行的占空比锁频环一起，开关反馈可在启动时实现稳健的频率和相位采集，并在发生大的相位和频率干扰时帮助子采样 PLL 恢复。提出了基于变压器的堆叠式 <inline-formula> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> 振荡器，以最大限度地降低功耗，同时提供足够的摆幅来驱动后续阶段。提出了一种截断恒定斜率数字时间转换器来提高功率效率，同时保持良好的线性度。所提出的小数-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> DPLL仅消耗265 <inline-formula> <tex-math notation="LaTeX">$mu ext{W}$ </tex-math></inline-formula>，同时实现2.8 ps的综合抖动和最坏情况 -52 dBc 的小数杂散，对应于 -237 dB 的品质因数 (FOM)。
This article proposes a fractional-<italic>N</italic> digital phase-locked loop (DPLL) that achieves a 265-<inline-formula> <tex-math notation="LaTeX">$mu ext{W}$ </tex-math></inline-formula> ultra-low-power operation. The proposed switching feedback can seamlessly change the DPLL from sampling operation to sub-sampling operation without disturbing the phase-locked state of the DPLL to reduce the number of building blocks that works at the oscillator frequency, leading to significant power reduction. With the reduced number of high-frequency circuits, scaling the reference frequency is fully used to reduce the power consumption of the DPLL. Together with an out-of-dead-zone detector and a duty-cycled frequency-locked loop running in the background, the switching feedback achieves robust frequency and phase acquisition at start-up and helps the sub-sampling PLL recover when large phase and frequency disturbances occur. A transformer-based stacked-<inline-formula> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> oscillator is proposed to minimize the power consumption while providing the sufficient swing to drive the subsequent stages. A truncated constant-slope digital-to-time converter is proposed to improve the power efficiency while retaining good linearity. The proposed fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> DPLL consumes only 265 <inline-formula> <tex-math notation="LaTeX">$mu ext{W}$ </tex-math></inline-formula> while achieving an integrated jitter of 2.8 ps and a worst case fractional spur of −52 dBc, which corresponds to a figure of merit (FOM) of −237 dB.