A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs
A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs
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DOI：
10.1145/2564922
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发表时间：
2014-02
期刊：
影响因子：
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通讯作者：
D. Xiang;Kele Shen
中科院分区：
文献类型：
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作者：
D. Xiang;Kele Shen
三维（3-D）技术为集成电路（ic）密度的增加提供了一种新的解决方案。在这项工作中，我们通过考虑通硅过孔（tsv）的互连开销，提出了用于3-D集成电路键前和键后测试的新型扫描架构。由于3d集成电路中的热点经常导致性能和可靠性问题，我们还开发了不同的键前和键后测试顺序方案，以避免使用可能使温度分布恶化的测试向量。实验结果表明，采用三维扫描树结构可将峰值温度降低20%。当与测试排序方案相结合时，三维扫描树可以进一步降低峰值温度30%以上。
The three-dimensional (3-D) technology offers a new solution to the increasing density of integrated circuits (ICs). In this work, we propose novel scan architectures for 3-D IC pre-bond and post-bond testing by considering the interconnection overhead of through-silicon-vias (TSVs). Since hotspots in 3-D ICs often cause performance and reliability issues, we also develop different test ordering schemes for prebond and postbond testing to avoid applying test vectors that could worsen the temperature distribution. Experimental results show that the peak temperature can be lowered by 20% with the 3-D scan tree architecture. When combined with the test ordering scheme, the 3-D scan tree can further reduce peak temperature by over 30%.