Bit error and soft error hardenable 7T/14T SRAM with 150-nm FD-SOI process
Bit error and soft error hardenable 7T/14T SRAM with 150-nm FD-SOI process
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DOI：
10.1109/irps.2011.5784596
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发表时间：
2011-04
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影响因子：
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通讯作者：
S. Yoshimoto;T. Amashita;S. Okumura;Kosuke Yamaguchi;M. Yoshimoto;H. Kawaguchi
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文献类型：
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作者：
S. Yoshimoto;T. Amashita;S. Okumura;Kosuke Yamaguchi;M. Yoshimoto;H. Kawaguchi
本文介绍了 150 nm FD-SOI 7T/14T（7 晶体管/14 晶体管）SRAM 测试芯片的误码率 (BER) 和软错误率 (SER) 改进的测量结果。 7T/14T SRAM的可靠性可以根据操作条件和应用通过控制信号动态改变。 14T可靠模式在14T单元中分配一位并同时提高读取操作中的BER和保留状态中的SER。我们使用 Synopsys TCAD 模拟器研究其错误率缓解机制。在我们的测量中，与 7T 正常模式相比，14T 可靠模式的最小工作电压提高了 100 mV，α 诱发的 SER 抑制了 80.0%，中子诱发的 SER 降低了 34.4%。
This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor / 14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.