Architectural Exploration to Enable Sufficient MTJ Device Write Margin for STT-RAM Based Cache
Architectural Exploration to Enable Sufficient MTJ Device Write Margin for STT-RAM Based Cache
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DOI：
10.1109/tmag.2012.2193589
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发表时间：
2012-04
影响因子：
2.1
通讯作者：
Hongbin Sun;Chuanyin Liu;Tai Min;Nanning Zheng;Tong Zhang
中科院分区：
文献类型：
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作者：
Hongbin Sun;Chuanyin Liu;Tai Min;Nanning Zheng;Tong Zhang
基于磁隧道结（MTJ）的自旋转矩传递RAM （STT-RAM）作为一种很有前途的非易失性存储技术，近年来受到了广泛的关注。然而，最近的设备研究表明，为了保持足够的MTJ写入余量以防止设备故障，随着内存单元大小的缩小，MTJ可能会受到非常规的高随机写入错误率（例如，10-3或以上）的影响。在本文中，我们的目标是开发一种STT-RAM缓存设计解决方案，该解决方案可以在较小的性能和实现成本下有效地容忍高MTJ写错误率，这使得保持足够的MTJ写余量变得更加容易，从而推动STT-RAM的可扩展性。使用完整的系统模拟器PTLsim和各种基准测试，我们表明所提出的架构设计可以很容易地适应MTJ写入错误率高达2%，而代价是处理器性能下降不到3%，硅面积开销不到10%，能耗开销可以忽略不计。
As a promising nonvolatile memory technology, magnetic tunnel junction (MTJ) based spin-torque transfer RAM (STT-RAM) has recently attracted much attention. However, recent device research suggested that, in order to maintain sufficient MTJ write margin to prevent device breakdown, MTJs may be subject to unconventionally high random write error rates (e.g., 10-3 and above) as memory cell size is being scaled down. In this paper, we aim to develop a STT-RAM cache design solutions that can effectively tolerate high MTJ write error rates at small performance and implementation cost, which makes it much easier to maintain sufficient MTJ write margin and hence push the STT-RAM scalability envelope. Using the full system simulator PTLsim and a variety of benchmarks, we show that the proposed architecture design can readily accommodate MTJ write error rate upto 2% at the penalty of less than 3% processor performance degradation, less than 10% silicon area overhead, and negligible energy consumption overhead.