Towards write-back aware software emulator for non-volatile memory

Towards write-back aware software emulator for non-volatile memory
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面向非易失性存储器的回写感知软件模拟器

DOI:
10.1109/nvmsa.2017.8064479
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发表时间:
2017
期刊:
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA2017)
影响因子:
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通讯作者:
Namiki Mitaro
Namiki Mitaro
中科院分区:
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文献类型:
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作者:
Koshiba Atsushi;Hirofuchi Takahiro;Akiyama Soramichi;Takano Ryousei;Namiki Mitaro

文献摘要

相似文献

诸如相变存储器之类的非易失性存储器(NVM)是未来低能耗和高容量存储系统的一项有前途的技术。 NVM 的众所周知的问题之一是其与 DRAM 等常见内存子系统不同的基本特性。特别是,NVM 写入延迟远高于 DRAM,而 NVM 读取延迟几乎与 DRAM 相同。延迟不对称会显着影响应用程序的性能。为了分析在 NVM 环境中运行的应用程序的行为,由于商业 NVM 产品数量有限,大多数研究人员使用仿真工具。然而,这些现有工具太慢,无法模拟大规模工作负载,或者太简单,无法模拟具有不对称读/写延迟的 NVM 上的应用程序行为。因此,本文提出了一种新的 NVM 仿真模型,该模型不仅轻量级,而且能够感知 NVM 读/写延迟差距。我们在商用英特尔处理器上实现了我们的原型。我们还评估了其准确性并针对实际基准进行了案例研究。结果表明,我们的原型可以根据实际工作负载的写入行为来模拟其执行时间,而现有的轻量级模拟模型会高估执行时间。
Non-volatile memory (NVM) such as phase change memory is a promising technology for future low-energy and high-capacity memory systems. One of the well-known issues of NVM is its fundamental characteristics that are different from common memory subsystems with DRAM. In particular, the NVM write latency is much higher than DRAM while the NVM read latency is almost the same as DRAM. The latency asymmetry affects the performance of applications significantly. For analyzing behavior of applications running on NVM environments, most researchers use emulation tools due to the limited number of commercial NVM products. However, these existing tools are too slow to emulate a large-scale workload or too simplistic to emulate the application behavior on NVM with asymmetric read/write latencies. This paper therefore proposes a new NVM emulation model that is not only light-weight but also aware of the NVM read/write latency gap. We implemented our prototype on a commercial Intel processor. We also evaluated its accuracy and performed case studies for practical benchmarks. The results show that our prototype can emulate the execution time of practical workloads according to their write behavior, while an existing light-weight emulation model over-estimates the execution time.