Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection
Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection
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DOI：
10.1007/s11432-008-0065-6
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发表时间：
2008-06
期刊：
影响因子：
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通讯作者：
F. Qiao;Huazhong Yang;Gang Huang;Hui Wang
中科院分区：
文献类型：
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作者：
F. Qiao;Huazhong Yang;Gang Huang;Hui Wang
本文提出了一种用于高速片上异步互连的新型低摆幅接口电路。它采用差分电平触发锁存器来恢复具有小于50 mV的超低摆幅电压的数字信号，并且接口电路的驱动器部分使用驱动器阵列方法针对低功耗进行了优化。该电路工作频率高达 500 MHz，采用 SMIC 0.18μm 1.8V 数字 CMOS 技术进行仿真和制造，功耗比之前报道的设计要低。
A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method. With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-μm 1.8-V digital CMOS technology, consumes less power than previously reported designs.