Surface integrity of silicon wafers in ultra precision machining
Surface integrity of silicon wafers in ultra precision machining
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DOI：
10.1007/s00170-005-2508-1
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发表时间：
2006-03
期刊：
影响因子：
--
通讯作者：
H. Young;H. Liao;H. Y. Huang
中科院分区：
文献类型：
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作者：
H. Young;H. Liao;H. Y. Huang
硅片是集成电路（IC）衬底中应用最广泛的材料。在形成晶圆之前，单晶硅锭必须经过一系列的加工过程，包括切片、研磨、表面研磨、边缘成型和抛光。该工艺的一个关键要求是在工件上产生直径达350毫米的极其平坦的表面。对于0.18 μm集成电路工艺，业界严格要求总厚度变化（TTV）小于15 μm。此外，在最后的蚀刻和抛光之前，表面应该是光滑的（Ra<10 nm），并且具有最小的亚表面损伤（<10 μm）。最终产品应具有无裂纹镜面，微粗糙度小于1.8 Å。本文通过实验研究了不同参数对硅片表面损伤的影响。
Silicon wafers are the most extensively used material for integrated circuit (IC) substrates. Before taking the form of a wafer, a single crystal silicon ingot must go through a series of machining processes, including slicing, lapping, surface grinding, edge profiling, and polishing. A key requirement of the processes is to produce extremely flat surfaces on work pieces up to 350 mm in diameter. A total thickness variation (TTV) of less than 15 μm is strictly demanded by the industry for an 0.18 μm IC process. Furthermore, the surfaces should be smooth (Ra<10 nm) and have minimum subsurface damage (<10 μm) before the final etching and polishing. The end product should have crack-free mirror surfaces with a micro-roughness less than 1.8 Å. In this paper, experiments are conducted to investigate the effects of various parameters on the subsurface damage of ground silicon wafers.