An efficient combinationality check technique for the synthesis of cyclic combinational circuits
An efficient combinationality check technique for the synthesis of cyclic combinational circuits
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一种用于循环组合电路综合的有效组合性检查技术
DOI：
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
Janet Roveda
中科院分区：
文献类型：
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作者：
Vineet Agarwal;N. Kankani;Ravishankar Rao;Sarvesh Bhardwaj;Janet Roveda
最近有人指出，循环电路不一定是顺序的，并且组合的循环拓扑通常比非循环拓扑具有更低的文字计数。然而，循环组合电路的合成是潜在的昂贵的，由于需要探索广泛的循环拓扑结构，并检查它们中的每一个的组合。我们首先得到给定布尔函数集的非循环实现。然后使用分支定界启发式算法，我们生成要检查组合性的循环电路。与早期复杂的组合性检查方法不同，我们的方法是检查这个循环电路是否在功能上等价于先前获得的非循环电路。在用所提出的方法合成循环电路时，我们观察到Berkeley sis软件包合成的非循环电路的文字计数（对于Espresso和LGS193基准测试）提高了45%。
It has been recently pointed out that cyclic circuits are not necessarily sequential, and cyclic topologies that are combinational generally have lower literal counts than their acyclic counterparts. However, the synthesis of cyclic combinational circuits is potentially expensive due to the need to explore a wide range of cyclic topologies and check each of them for combinationality. We first obtain the acyclic implementation of the given set of Boolean functions. Then using a branch-and-bound heuristic, we generate cyclic circuits that are to be checked for combinationality. Unlike earlier complex methods for combinationality check, our approach is to check whether this cyclic circuit is functionally equivalent to the acyclic circuit obtained earlier. While synthesizing cyclic circuits with the proposed method, we observed up to 45% improvements in the literal count (for Espresso and LGsynth93 benchmarks) over the acyclic circuit synthesized by the Berkeley sis package.