Realizing high-voltage junction isolated LDMOS transistors with variation in lateral doping
Realizing high-voltage junction isolated LDMOS transistors with variation in lateral doping
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DOI：
10.1109/ted.2004.839104
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发表时间：
2004-12-01
影响因子：
3.1
通讯作者：
Narayanan, EMS
中科院分区：
文献类型：
--
作者：
Hardikar, S;Tadikonda, R;Narayanan, EMS
使用完全注入的 CDMOS 工艺在结隔离技术中演示了漂移区横向掺杂 (VLD) 变化的高压横向扩散金属氧化物半导体 (LDMOS) 晶体管。 VLD 剖面是通过使用先前报道的分析方法来实现的。通过仿真和实验验证了分析模型。结果表明，与均匀掺杂相比，对于给定的漂移长度，使用 VLD 曲线可以获得更高的击穿电压，同时在击穿电压和比导通电阻之间提供良好的折衷。
High-voltage lateral diffused metal-oxide semiconductor (LDMOS) transistors with a variation in the lateral doping (VLD) of drift regions are demonstrated in junction isolation technology using a fully implanted CDMOS process. The VLD profile is realized by using an analytical approach reported previously. The analytical model is verified through simulations and experiment. Results indicate that higher breakdown voltages can be achieved for a given drift length using a VLD profile in comparison to uniform doping while offering a good tradeoff between breakdown voltage and specific on-resistance.