Performance and power consumption analysis of memory efficient 3D network-on-chip architecture
Performance and power consumption analysis of memory efficient 3D network-on-chip architecture
复制标题
内存高效 3D 片上网络架构的性能和功耗分析
DOI：
10.1109/icca.2013.6565107
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
Shuzhuan He
中科院分区：
文献类型：
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作者：
Xiao Yu;Li Li;Yuang Zhang;H. Pan;Shuzhuan He
近年来，随着3DIC技术和片上网络(NoC)技术的快速发展，3DNoC应运而生，并受到越来越多研究者的关注。但是，存储组织和功耗问题已经成为3D片上网络设计中的两大挑战。为了获得更好的性能和更低的功耗，本文提出了三种内存高效的3D NoC体系结构：核、角点和窗口。利用系统建模语言SystemC搭建了3D片上网络的仿真平台，对其性能进行了评估。实验结果表明，与其他两种传统的3D NoC存储结构相比，本文提出的两种3D NoC存储结构分别具有更好的性能和更低的功耗。
With the rapid development of the technology of 3D IC and Network-on-Chip (NoC) technology, 3D NoC emerged and drew more and more attention of researchers in recent years. But the issues of memory organization and power consumption have become two great challenges in the design of 3D NoC. This paper proposed three kinds of memory efficient 3D NoC architecture called core, corner and windows in order to achieve better performance and lower power consumption for the system. A simulation platform of 3D NoC is built with a systematical modeling language -SystemC to evaluate the performance. The experiment result shows that when compared with other two traditional 3D NoC memory architecture perlayer and mixed, two 3D NoC architectures we proposed can gain better performance and lower power consumption respectively.