A 65 nm 2-Billion Transistor Quad-Core Itanium Processor
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor
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DOI：
10.1109/jssc.2008.2007150
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发表时间：
2009
影响因子：
5.4
通讯作者：
B. Stackhouse;Sal Bhimji;C. Bostak;D. Bradley;B. Cherkauer;J. Desai;Erin Francom;M. Gowan;P. Gronowski;Dan Krueger;Charles Morganti;Steve Troyer
中科院分区：
文献类型：
--
作者：
B. Stackhouse;Sal Bhimji;C. Bostak;D. Bradley;B. Cherkauer;J. Desai;Erin Francom;M. Gowan;P. Gronowski;Dan Krueger;Charles Morganti;Steve Troyer
本文介绍了一种在65 nm工艺实现的8层Cu互连的Itanium处理器。21.5 mm × 32.5 mm芯片具有2.05 B晶体管。该处理器具有四个双线程内核，30 MB缓存和一个在105摄氏度下以2.4 GHz运行的系统接口。高速串行互连允许96 GB/s的峰值处理器到处理器带宽和34 GB/s的峰值内存带宽。
This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105degC . High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s.