High-Performance Split-Gate-Enhanced UMOSFET With Dual Channels
High-Performance Split-Gate-Enhanced UMOSFET With Dual Channels
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DOI:
10.1109/ted.2017.2665589
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发表时间:
2017-04
影响因子:
3.1
通讯作者:
Ying Wang;Chenghao Yu;Mengqing Li;Fei Cao;Yan-juan Liu
中科院分区:
文献类型:
--
作者:
Ying Wang;Chenghao Yu;Mengqing Li;Fei Cao;Yan-juan Liu
This paper presents an optimized split-gate-enhanced trench MOSFET with dual channels (DSGE-UMOS). The 2-D device simulator ATLAS is used to investigate the characteristics of the proposed structure. When compared with the conventional SGE-UMOS, the optimized device shows a significant reduction in the specific on-resistance ( ${R}_{ {\mathrm{\scriptscriptstyle ON}}\text {-sp}}$ ) at a breakdown voltage of 120 V, which is due to the adoption of an additional p-type well region. Furthermore, the proposed structure can also enhance the single-event burnout (SEB) survivability. Based on the DSGE-UMOS, the hardened DSGE-UMOS (an n-type buffer layer is added between the epitaxial layer and substrate layer) is also investigated that the addition of the buffer layer can improve the SEB performance a lot.