Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor
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DOI：
10.1109/ismvl.2007.14
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发表时间：
2007-05
期刊：
影响因子：
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通讯作者：
H. Shirahama;A. Mochizuki;T. Hanyu;M. Nakajima;K. Arimoto
中科院分区：
文献类型：
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作者：
H. Shirahama;A. Mochizuki;T. Hanyu;M. Nakajima;K. Arimoto
针对多核单指令多数据(SIMD)处理器，提出了一种基于四值差分逻辑的高速、低功耗、紧凑的处理单元(PE)。作为ALU的关键路径的两位加法被归因于通过使用多值电流模式(MVCM)差分逻辑电路直接执行的一位四进制加法。用MVCM差分逻辑电路简单地实现了一位四值触发器。在0.18微米的CMOSHSPICE模拟中，与相应的CMOS型电路进行了比较，验证了所提出的四值PE的有效性。
A high-speed, low-power and compact processing element (PE) using quaternary differential logic is proposed for a multi-core single-instruction multiple-data (SIMD) processor. A two-bit addition which is the critical path of the ALU is attributed to a one-digit quaternary addition that is directly performed by using multiple-valued current- mode (MVCM) differential logic circuitry. A one-digit quaternary flip-flop is also simply implemented by using the MVCM differential logic circuitry. The efficiency of the proposed quaternary PE is demonstrated using 0.18 mum CMOS HSPICE simulation in comparison with a corresponding CMOS implementation.