6.1 A 3.9µm Pixel Pitch VGA Format 10b Digital Image Sensor with 1.5-Transistor/Pixel
6.1 A 3.9µm Pixel Pitch VGA Format 10b Digital Image Sensor with 1.5-Transistor/Pixel
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6.1 具有 1.5 晶体管/像素的 3.9μm 像素间距 VGA 格式 10b 数字图像传感器
DOI：
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
S. Inoue
中科院分区：
文献类型：
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作者：
Hidekazu Takahashi;M. Kinoshita;Kazumichi Morita;Takahiro Shirai;Toshiaki Sato;Takayuki Kimura;H. Yuzurihara;S. Inoue
该数字cmos图像传感器采用0.35µm 1P 2m cmos工艺制造，采用专门的埋入式光电二极管附加步骤，具有完整的电荷转移能力。该图像传感器输出自动获取的10b并行数字信号。图6.1.1显示了由703x499像素、列噪声消除器和扫描电路组成的CMOS图像传感器的框图。该图像传感器还包括电压调节器、时序发生器、AGC、10b DAC和10b流水线ADC。该图像传感器使用单个主时钟运行，频率高达12.27 MHz。可编程功能包括使用恒定频率主时钟的可变帧速率、电子曝光控制、暗级别控制和渐进式或监视模式。总可编程增益为30分贝。图6.1.2显示了一个像素的原理图和一个时序图。M1、M2、M3和M4是由垂直移位寄存器(VSR)控制的传输门，并且将信号电荷从光电二极管传输到浮动扩散FD。通过单独打开每1H周期的M1、M2、M3和M4，逐行扫描成为可能。M5是用于FD的复位门，并且用作行选择门；因此，不需要常规的行选择门。晶体管M6是一个放大器。传统的具有完全电荷转移能力的cmos图像传感器需要为每个光电二极管配置四个晶体管。这种像素架构只对四组光电二极管使用两个晶体管和一个传输门，或每个光电二极管使用1.5个晶体管。在信号电荷从光电二极管完全转移到FD后，曝光开始。在此光电二极管重置中，不会出现热重置噪声，因为它是完全耗尽重置。在曝光期间，光电流在光电二极管的耗尽层中积累。在读出期间，通过同时打开M7和M8并激活放大器，将FD电势从GND提高到VVRH。恒流源通过打开M9连接到放大器，从而使源极跟随器读出成为可能。当M1导通时，信号电荷完全从光电二极管(PD1)转移到FD。在电荷转移期间，由于其他光电二极管(PD2、PD3和PD4)的转移栅极关闭，所以其他光电二极管的信号电荷不转移。在M1接通之前和之后读出暗信号和光信号。信号读出后，通过打开两个开关，将FD电势固定为GND
The digital CMOS image sensor is fabricated using a 0.35µm 1P 2M CMOS process with specialized add-on steps for the buried photodiode with complete charge transfer capability. This image sensor outputs auto-gained 10b parallel digital signals. Figure 6.1.1 shows the block diagram of the CMOS image sensor which consists of 703x499 pixels with a column noise canceler and scanning circuits. The image sensor further includes a voltage regulator, a timing generator, an AGC, a 10b DAC and a 10bpipelined ADC. The image sensor operates with a single master clock runs at frequencies of up to 12.27MHz. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, dark level control and progressive or monitoring mode. The total programmable gain of 30dB is available. Figure 6.1.2 shows the schematic of a pixel and a timing diagram. M1, M2, M3 and M4 are transfer gates controlled by vertical shift register (VSR), and transfer signal charges from the photodiode to floating diffusion FD. Progressive scanning becomes possible by M1, M2, M3 and M4 turn on every 1H period independently. M5 is the reset gate for FD and is used as a row select gate; therefore, a conventional row select gate is unnecessary. Transistor M6 is an amplifier. The conventional CMOS image sensor with complete charge transfer capability needs four transistors for each photodiode. This pixel architecture uses only two transistors for four sets of photodiodes and a transfer gate or 1.5 transistors per photodiode. The exposure begins after signal charges are completely transferred from a photodiode to FD. In this photodiode reset, thermal reset noise does not occur because it is a full depletion reset. During the exposure period, photo current is accumulated in the depletion layer of the photodiode. In the readout period, the FD potential is raised from GND to VVRH by turning M7 and M8 on both, and activating the amplifier. The constant current source is connected to the amplifier by turning on M9 making possible source follower readout. When M1 turns on, the signal charges are completely transferred from the photodiode (PD1) to FD. During charge transfer period, the signal charges of the other photodiodes are not transferred as the transfer gates of other photodiodes (PD2, PD3 and PD4) are off. The dark signal and the photo signal are read out before and after M1 turns on. After the signal readout, the FD potential is fixed to GND by turning on both