Power distribution network (PDN) design and analysis of a single and double-sided high bandwidth memory (HBM) interposer for 2.5D Terabtye/s bandwidth system
Power distribution network (PDN) design and analysis of a single and double-sided high bandwidth memory (HBM) interposer for 2.5D Terabtye/s bandwidth system
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用于 2.5D Terabtye/s 带宽系统的单双面高带宽存储器 (HBM) 内插器的配电网络 (PDN) 设计和分析
DOI：
10.1109/isemc.2016.7571620
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发表时间：
2016
期刊：
影响因子：
--
通讯作者：
Joungho Kim
中科院分区：
文献类型：
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作者：
Kyungjun Cho;Youngwoo Kim;Subin Kim;Hyunsuk Lee;Sumin Choi;Heegon Kim;Joungho Kim
三维堆叠高带宽存储器（HBM）成为一种很有前途的解决方案，以满足处理器的存储器带宽。由于其独特的存储器架构，包括大量的输入/输出（I/O），这是不可避免的雇员硅基中介层。因此，HBM中介层的配电网络（PDN）设计和分析成为保证整个存储器接口性能的重要步骤之一。由于半导体行业的后端工艺（BEOL）技术应用于HBM中介层，因此需要控制金属密度和管理晶片翘曲。因此，由于金属密度的限制，我们设计并分析了HBM中介层的网状和网格型PDN。此外，我们还设计和分析了PDN的单面和双面中介层。因为，与单面插入器相比，双面插入器具有翘曲管理的优势。为了抑制同步开关噪声（SSN），必须正确分析具有去耦电容方案的PDN阻抗。本文分别设计了五层和六层的单面和双面HBM中介层，分析了含硅通孔（TSV）的PDN阻抗。在100 MHz ~ 20 GHz频率范围内，对HBM中介层的PDN阻抗进行了仿真分析。基于所设计的HBM中介层，我们展示了HBM中介层在降低PDN阻抗方面的巨大潜力，以通过金属-绝缘体-金属（MIM）去耦电容来抑制SSN。
A 3-D stacked high bandwidth memory (HBM) becomes a promising solution to satisfy the memory bandwidth for the processor. Due to its unique memory architecture that consists of tremendous number of input/output (I/O), it is inevitable to employee Silicon based interposer. Therefore, power distribution network (PDN) design and analysis of HBM interposer becomes one of the important step to guarantee the performance of an entire memory interface. Since the back end of line (BEOL) process technology of a semiconductor industry is applied for HBM interposer, the control of a metal density and the management of wafer warpage are required. Therefore, we designed and analyzed meshed and grid type of PDN for HBM interposer because of the limit of a metal density. In addition, we also designed and analyzed PDN both a single- and double-sided interposer. Because, a double-sided interposer has an advantage of a warpage management compared to a single-sided interposer. For the suppression of simultaneous switching noise (SSN), PDN impedance with a decoupling capacitor scheme must be properly analyzed. In this paper, a single- and double-sided HBM interposer is designed with the five layers and six layers respectively to analyze PDN impedance including though-Silicon-via (TSV). PDN impedance of HBM interposer is simulated and analyzed in the frequency range from 100 MHz to 20 GHz. Based on the designed HBM interposer, we shows the great potential of HBM interposer in terms of the reduction of PDN impedance to suppress SSN with a metal-insulator-metal (MIM) decoupling capacitor.