Geyser-2: The second prototype CPU with fine-grained run-time power gating
Geyser-2: The second prototype CPU with fine-grained run-time power gating
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Geyser-2：第二个具有细粒度运行时电源门控的原型 CPU
DOI：
10.1109/aspdac.2011.5722310
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
Masaaki Kondo
中科院分区：
文献类型：
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作者：
Lei Zhao;Daisuke Ikebuchi;Yoshiki Saito;M. Kamata;Naomi Seki;Y. Kojima;H. Amano;S. Koyama;T. Hashida;Y. Umahashi;D. Masuda;K. Usami;K. Kimura;M. Namiki;S. Takeda;Hiroshi Nakamura;Masaaki Kondo
Geyser-2 是第二个原型 MIPS CPU，它提供由指令控制的细粒度运行时电源门控 (PG)。 Geyser-1[1]，第一个原型仅提供细粒度的运行时PG核心。虽然它在实际芯片上展示了泄漏功率的降低，但由于 I/O 速度的限制，工作频率仅限于 60MHz。具有缓存和 TLB 机制的 Geyser-2 的实现表明：（1）运行时 PG 至少可以在 200MHz（嵌入式系统常用时钟）下工作，（2）它在带有操作系统的实际应用程序环境中也很高效。
Geyser-2 is the second prototype MIPS CPU which provides a fine-grained run-time power gating (PG) controlled by instructions. Geyser-1[1], the first prototype only provides the fine-grained run-time PG core. Although it demonstrated the leakage power reduction on a real chip, the operational frequency is limited at 60MHz because of the limitation of the I/O speed. Geyser-2 with cache and TLB mechanism is implemented to show (1) run-time PG works at least with 200MHz which is commonly used clock for embedded systems, and (2) it is also efficient on the environment with real application programs with an operating system.