An Introduction to Systolic Architectures
An Introduction to Systolic Architectures
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脉动架构简介
DOI：
10.1007/3-540-18203-9_13
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发表时间：
1986
影响因子：
2.9
通讯作者：
P. Quinton
中科院分区：
文献类型：
--
作者：
P. Quinton
VLSI技术的快速发展需要新的架构范式。在利用这一进化的众多尝试中，由Kung和Leiserson提出的收缩阵列概念已被证明是最成功的一个。收缩数组背后的概念并不新鲜。可以将收缩数组视为SIMD和管道架构特征的组合。在前者中，收缩阵列继承了结构和操作的规律性。对于后者，它们共享常规的数据循环和通过将计算分成小步骤来获得效率的能力。收缩数组之所以具有独创性，是因为系统地使用了一些在旧架构范例中已经存在的思想，以便正确地响应VLSt技术带来的新挑战。在这方面，Mead和Conway的基础VLSI教科书用了半章来讨论这个主题是非常重要的。自从早期关于收缩数组的论文（例如[4]和[11]，它们是该主题的优秀介绍性论文）以来，人们的兴趣从未停止过，而且，在这个领域所做的工作越来越多。在本文中，我们想对最近的趋势提供一个描述。我们首先在第2节给出关于收缩数组的基本例子和概念。在第3节中，我们将介绍更复杂的算法，并尝试给出这种架构的灵活性的概念。第4节专门介绍合成收缩阵列的方法。最后，第5节通过检查收缩阵列引起的问题来总结。
Rapid advance in VLSI technology calls for new architectural paradigms. Among the numerous attemps to take advantage of this evolution, the introduction by Kung and Leiserson [10] of the systolic array concept has proven to be one of the most successful. The concepts underlying systolic arrays are not new. One can think of systolic arrays as a combination of the SIMD and the pipeline architectures characteristics. Of the former one, systolic arrays have inherited the regularity of both structure and operations. With the latter, they share the regular data circulation and the capacity to gain efficiency by splitting computations into small steps. What makes clearly systolic arrays original is the systematic use of a few ideas that were already present in older architectural paradigms, in order to respond properly to the new challenge posed by VLSt technology. To this respect, it is highly significant that the basic VLSI text book of Mead and Conway [15] devotes half a chapter to this topic.Since the early papers on systolic arrays (see for example [4] and [11] that are excellent introductory papers to the subject), the interest has never ceased, and moreover, there is an increasing amount of work done in this domain. In this paper, we would like to provide a description of recent tendencies. We first start by giving in section 2 basic examples and notions on systolic arrays. In section 3, more complex algorithms are presented, and we try to give an idea of the flexibility of this kind of architectures. Section 4 is devoted to methods for synthesizing systolic arrays. Finally, section 5 concludes by examining issues raised by systolic arrays.