A high-speed oscillator-based truly random number source for cryptographic applications on a Smart Card IC
A high-speed oscillator-based truly random number source for cryptographic applications on a Smart Card IC
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DOI：
10.1109/tc.2003.1190581
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发表时间：
2003-04-01
影响因子：
3.7
通讯作者：
Varanonuovo, M
中科院分区：
文献类型：
--
作者：
Bucci, M;Germani, L;Varanonuovo, M
本文介绍了一种适合于集成在智能卡微控制器中的高速IC随机数源宏单元的设计。利用振荡器采样技术和抖动振荡器，它具有放大的热噪声源已被设计，以增加输出吞吐量和所生成的比特序列的统计质量。振荡器反馈环作为噪声放大器的失调补偿，从而解决了此类电路中的主要问题之一。所提出的系统的数值模型已被开发，它允许我们进行连续位之间的输出流的转移概率的解析表达式。一个原型芯片已在一个标准的数字0.18妈妈n阱CMOS工艺，具有10Mbps的吞吐量，并满足NIST的FIPS和相关性为基础的随机性测试。宏单元面积（不包括焊盘）为0.0016mm（2）（184 μ m × 86 μ m），并且已经测量到2.3mW的功耗。
The design of a high-speed IC random number source macro-cell, suitable to be integrated in a Smart Card microcontroller, is presented. The oscillator sampling technique is exploited and a jittered oscillator which features an amplified thermal noise source has been designed in order to increase the output throughput and the statistical quality of the generated bit sequences. The oscillator feedback loop acts as an offset compensation for the noise amplifier, thus solving one of the major issues in this kind of circuit. A numerical model for the proposed system has been developed which allows us to carry out an analytical expression for the transition probability between successive bits in the output stream. A prototype chip has been fabricated in a standard digital 0.18mum n-well CMOS process which features a 10Mbps throughput and fulfills the NIST FIPS and correlation-based tests for randomness. The macro-cell area, excluding pads, is 0.0016mm(2) (184mum x 86mum) and a 2.3mW power consumption has been measured..