A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM
A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM
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适用于 512 Mb 2.0 Gb/s/引脚 GDDR3 和 2.5 Gb/s/引脚 GDDR4 SDRAM 组合的宽范围混合模式 DLL
DOI：
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发表时间：
2008
影响因子：
5.4
通讯作者：
B. Keeth
中科院分区：
文献类型：
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作者：
Feng Lin;Roman A. Royer;Brian Johnson;B. Keeth
本文介绍了一种用于512 Mb图形SDRAM的混合模式延迟锁定环（MDLL）。MDLL通过应用时钟分频和模拟相位产生（APG）将其锁定范围扩展到千兆赫领域。来自MDLL的分频时钟用于时钟逻辑和跟踪SDRAM中的确定性访问延迟。简要讨论了使用分频多相时钟进行逻辑运算的一些副作用和优点。还公开了一种基于所提出的MDLL的低功率时钟分配网络（CDN）。MDLL采用1.5 V 95 nm三层金属CMOS工艺制造，在GDDR4模式和1 GHz时钟下，实测RMS抖动为4.6 ps，峰峰值抖动为38 ps。整个基于MDLL的CDN在800 MHz和1.5 V时的功耗为107 mW。
A mixed-mode delay-locked loop (MDLL) for a 512 Mb graphics SDRAM is presented in this paper. The MDLL extends its lock range into the gigahertz realm by applying clock division and analog phase generation (APG). The divided clock from the MDLL is used for clocking logic and tracking deterministic access latency in the SDRAM. A short discussion of some of the side effects and advantages of using a divided, multi-phase clock for logic operation is presented. A low-power clock distribution network (CDN) based on the presented MDLL is also disclosed. Fabricated in a 1.5 V 95 nm triple-metal CMOS process, the MDLL achieves a measured RMS jitter of 4.6 ps and peak-to-peak jitter of 38 ps at GDDR4 mode with a 1 GHz clock. Power consumption for the entire MDLL-based CDN is 107 mW at 800 MHz and 1.5 V.