An interconnect-aware delay model for dynamic voltage scaling in NM technologies
An interconnect-aware delay model for dynamic voltage scaling in NM technologies
复制标题
用于 NM 技术中动态电压缩放的互连感知延迟模型
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
Y. Savaria
中科院分区：
文献类型：
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作者：
H. Zarrabi;A. Al;Y. Savaria
采用具有动态电压调节(DVS)功能的微系统是降低其能耗的有效设计方案。随着高性能和低能耗的同时被需要，这种设计技术的重要性不断增长。现有的支持DVS的电源管理单元(PMU)主要依赖于对CMOS逻辑有效的延迟模型。在这项工作中，我们表明，这可能会导致受DVS影响的微系统的不适当设计和使用，因为互连延迟已经成为总延迟的主要部分。针对这一设计问题，我们提出了一种改进的时延模型，该模型考虑了互连寄生元件的影响，适合于PMU在纳米(Nm)技术中执行的DVS的精确建模、设计和执行。HSPICE仿真结果表明，该时延模型在预测四段式全局H-Tree时钟分配网络的性能时，具有较高的精度。真实延迟对预测性能的误差最高可减少到原来的4倍。
Employing microsystems with Dynamic Voltage Scaling (DVS) is an effective design solution to alleviate their energy consumption. The importance of such design technique keeps growing as both high-performance and low-energy consumption are simultaneously desirable. Existing Power Management Units (PMUs) that support DVS, mainly rely on the delay models valid for CMOS logic. In this work, we show that this may result into improper design and utilization of microsystems subject to DVS; as interconnect delay has become the dominant fraction of the total delay. In accordance with this design concern, we propose a modified delay model which encompasses the effect of interconnect parasitic components, and is suitable for accurate modeling, design and execution of DVS performed by PMUs in nanometer (nm) technologies. HSPICE simulations confirm that the proposed delay model is much more accurate when predicting the performance of a 4-section global H-Tree clock distribution network subject to voltage scaling. The error on predicted performance from true delays is reduced by up to a factor of 4.