RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology

RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology
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RTA 驱动的芯片内阶段延迟变化以及 65nm 技术的参数灵敏度

DOI：
10.1109/vlsit.2006.1705271
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发表时间：
2006
期刊：
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.
影响因子：
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通讯作者：
B. Walsh
B. Walsh
中科院分区：
--
文献类型：
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作者：
I. Ahsan;N. Zamdmer;O. Glushchenkov;R. Logan;E. Nowak;H. Kimura;J. Zimmerman;G. Berg;J. Herman;E. Maciejewski;A. Chan;A. Azuma;S. Deshpande;B. Dirahoui;G. Freeman;A. Gabor;M. Gribelyuk;S. Huang;M. Kumar;K. Miyamoto;D. Mocuta;A. Mahorowala;E. Leobandung;H. Utomo;B. Walsh

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我们首次详细研究了由毫米级快速热退火(RTA)的变化所驱动的65 nm工艺的CMOS反相器延迟的芯片内变化(IDV)。我们发现，VT和REXT的变化是IDV延迟和泄漏的主要原因，并且受LAMP RTA斜坡率的调制。我们表明，逆变器延迟与器件图案密度的预测反射率的毫米级变化有很好的相关性
We report, for the first time, a detailed study of intra-die variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA). We find that variation in VT and REXT accounts for most of the IDV in delay and leakage and is modulated by lamp RTA ramp rate. We show a good correlation of inverter delay to mm-scale variation in the predicted reflectivity of the device pattern densities