Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure
Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure
复制标题
具有网状连接蜂窝阵列结构的无程序计数器位串行现场可编程VLSI处理器
DOI：
10.1109/isvlsi.2004.1339547
复制
发表时间：
2004
期刊：
影响因子：
--
通讯作者：
M. Kameyama
中科院分区：
文献类型：
--
作者：
Naotaka Ohsawa;O. Sakamoto;M. Hariyama;M. Kameyama
本文提出了一种基于位串行网格连接单元阵列的现场可编程VLSI处理器（FPVLSI），它降低了可编程互连网络的复杂性。单元能够执行操作、存储中间结果以及控制位串行操作。为了有效地实现这三个功能，该单元由基于移位寄存器的查找表组成。此外，直接分配的控制/数据流图（CDFG）中只有一个单一的节点被映射到一个单一的细胞，使互连的复杂性大大降低。采用0.18/spl μ/mCMOS设计规则设计了64单元的FPVLSI。在一个典型的应用中，FPVLSI的估计性能被评估为比传统的FPGA高9倍。
This paper proposes a field programmable VLSI processor (FPVLSI) based on a bit-serial mesh-connected cellular array that reduces complexity of a programmable interconnection network. A cell is capable of performing operations, storing intermediate results, and controlling bit-serial operations. To implement these three functions efficiently, the cell consists of shift-register-based lookup tables. Moreover, direct allocation of a control/data flow graph (CDFG) is employed where only a single node in a CDFG is mapped into a single cell so that the interconnection complexity is greatly reduced. The FPVLSI with 64 cells is designed in a 0.18/spl mu/m CMOS design rule. The estimated performance of the FPVLSI is evaluated to be 9 times higher than that of the conventional FPGA in a typical application.