A Digital Readout Integrated Circuit Based on Pixel-Level ADC Incorporating On-Chip Image Algorithm Calibration for IRFPA
A Digital Readout Integrated Circuit Based on Pixel-Level ADC Incorporating On-Chip Image Algorithm Calibration for IRFPA
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DOI：
10.1109/jsen.2023.3300874
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发表时间：
2023-09
影响因子：
4.3
通讯作者：
Yan-an Zeng;Shiheng Yang;Yueduo Liu;Rongxin Bao;Zihao Zhu;Jiahui Lin;Xiong Zhou;Yong Chen;J. Yin;Pui-in Mak;Qiang Li
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文献类型：
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作者：
Yan-an Zeng;Shiheng Yang;Yueduo Liu;Rongxin Bao;Zihao Zhu;Jiahui Lin;Xiong Zhou;Yong Chen;J. Yin;Pui-in Mak;Qiang Li
本文介绍了一种基于像素级18位模数转换器（ADC）的数字读出集成电路（DROIC），该电路具有完全片上图像算法校准功能，可用于红外焦平面阵列（IRFPA）。这种片上校准包括坏像素补偿、非均匀性校正和背景减除，其被实现以避免片上存储器存储以节省功率和面积。建议的DROIC是在一个标准的40纳米CMOS工艺制造，它具有一个640\times512 $的阵列尺寸与30- $\mu \text{m}$像素间距。在1.1 V电源电压下，单像素ADC的功耗小于0.7 W，数据速率和动态范围得到了提高，噪声等效温差（NEDT）为1.8 mK，峰值信噪比（SNR）为90.1 dB。测试比较表明，当启用校准时，图像质量得到显着改善。它是DROIC报告的最高集成度，具有完全片内校准和图像质量增强算法。
This article presents a digital readout integrated circuit (DROIC) with fully ON-chip image algorithm calibration based on the pixel-level 18-bit analog-to-digital converter (ADC) for infrared focal plane array (IRFPA) applications. Such ON-chip calibrations include bad pixel compensation, nonuniformity correction, and background subtraction, which are implemented to avoid ON-chip memory storage for saving power and area. The proposed DROIC was fabricated in a standard 40-nm CMOS process, and it features a $640\times512$ array size with a 30- $\mu \text{m}$ pixel pitch. The power consumption of a single-pixel ADC is less than $0.7 \mu \text{W}$ under a supply of 1.1 V. The data rate and the dynamic range are improved and it achieved a noise equivalent differential temperature (NEDT) of 1.8 mK and a peak signal-to-noise ratio (SNR) of 90.1 dB. A test comparison exhibits that the image quality is improved significantly when the calibration is enabled. It is the highest integration level reported DROIC, with fully ON-chip calibration and image-quality enhancement algorithm.