Process technology scaling in an increasingly interconnect dominated world
Process technology scaling in an increasingly interconnect dominated world
复制标题
在日益互联的世界中扩展工艺技术
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
J. Torres
中科院分区：
文献类型：
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作者：
J. Clarke;Christopher George;C. Jezewski;A. M. Caro;D. Michalak;J. Torres
由互连系统施加的RC延迟和功率限制可以随着尺寸缩小而以越来越严重的方式促成差的电路性能。电阻比技术的比例因子增加得更快，并且电容改进受到组装的堆叠的机械要求的限制。总的来说，这些在芯片上的局部和全局信息传输中引起瓶颈。正在探索新的沉积方法和新的导体材料作为增加导电横截面积的手段。分子有序化是同时提供电容和机械强度的机会。尽管有这些改进路径，但需要一种更全面的互连设计方法，其中应用和微架构对RC缩放约束的容忍度更高。
The RC delay and power restrictions imposed by the interconnect system can contribute to poor circuit performance in an increasingly severe manner as dimensions shrink. Resistances are increasing faster than the scale factor of the technology and capacitance improvements are constrained by mechanical requirements of the assembled stack. Collectively, these cause a bottleneck in both local and global information transfer on a chip. Novel deposition methods and novel conductor materials are being explored as means to increase conductive cross sectional area. Molecular ordering is an opportunity to simultaneously deliver capacitance and mechanical strength. Despite these improvement paths, a more holistic approach to interconnect design is needed, where the application and micro architecture are more tolerant of RC scaling constraints.