Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology
Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology
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DOI：
10.1109/vts.2018.8368651
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发表时间：
2018-04
期刊：
影响因子：
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通讯作者：
Kexin Yang;Taizhi Liu;Rui Zhang;L. Milor
中科院分区：
文献类型：
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作者：
Kexin Yang;Taizhi Liu;Rui Zhang;L. Milor
本文针对FinFET技术的前端（FEOL）时间相关介电击穿（TDDB）和新出现的中间线（MOL）时间相关介电击穿提出了一个寿命模拟器。针对数字电路和微处理器的目标磨损机制，提出了一种寿命评估流程，并详细讨论了相关的易损特征提取算法。我们的模拟器结合了详细的电应力，温度，线宽的每个标准单元内的数字电路和微处理器。此外，FEOL TDDB和MOL TDDB寿命在TDDB寿命的计算中被合并。电路设计人员可以使用由此产生的寿命信息来指导和改进他们的电路，使其更加强大和可靠。
This paper presents a lifetime simulator for both Front-End-of-Line (FEOL) time dependent dielectric breakdown (TDDB) and the newly emerging Middle-of-Line (MOL) time dependent dielectric breakdown for FinFET technology. A lifetime assessment flow for digital circuits and microprocessors is proposed for the target wearout mechanisms, and its associated vulnerable feature extraction algorithms are discussed in detail. Our simulator incorporates the detailed electrical stress, temperature, linewidth of each standard cell within the digital circuit and microprocessor. Also, FEOL TDDB and MOL TDDB lifetimes are combined in the calculation of TDDB lifetime. Circuit designers can use the resulting lifetime information to guide and improve their circuits to make them more robust and reliable.