Complete VLSI Implementation of Improved Low Complexity Chase Reed-Solomon Decoders
Complete VLSI Implementation of Improved Low Complexity Chase Reed-Solomon Decoders
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改进的低复杂度 Chase Reed-Solomon 解码器的完整 VLSI 实现
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发表时间：
2011
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通讯作者：
Wei An
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作者：
Wei An
本论文提出一个完整的RS码低复杂度Chase译码器之积体电路设计。这是在已发表的研究中首次尝试在电路级实现LCC解码器。本文在与夏威夷大学联合研究的基础上，提出了几种降低LCC译码器复杂度的新技术，并将其应用于RS [255，239，17]（LCC 255）和RS [31，25，7]（LCC 31）码的VLSI设计中。算法的主要改进是在测试向量的子集上进行插值，以避免冗余解码。同时，对分解公式进行了修正，避免了以往研究中忽略的计算量过大的问题。为了保持算法改进的有效性，我们发现有必要采用系统的消息编码，而不是在以前的工作中使用的插值解码器的评估映射编码。LCC 255和LCC 31解码器均采用90 nm CMOS工艺实现，面积分别为1.01mm2和0.255mm2。仿真结果表明，在1.2V电源电压下，最大吞吐量分别为2.5Gbps和1.3Gbps时，能量效率分别为67 pJ/bit和34 pJ/bit。提出的算法变化，结合优化的宏和微架构，可使复杂性降低70%（以门数衡量）。这种新的LCC设计还实现了17倍的能源效率比标准的大通解码器（预计从最近报道的里德所罗门解码器实现）相同的面积，延迟和吞吐量。两种解码器的比较将显著更高的解码能量成本与更好的解码性能联系起来。我们定量地计算了LCC 255的调整面积是LCC 31的7.5倍时的解码增益成本。论文指导：弗拉基米尔M.职称：副教授
This thesis presents a complete VLSI design of improved low complexity chase (LCC) decoders for Reed-Solomon (RS) codes. This is the first attempt in published research that implements LCC decoders at the circuit level. Based on the joint algorithm research with University of Hawaii, we propose several new techniques for complexity reduction in LCC decoders and apply them in the VLSI design for RS [255, 239,17] (LCC255) and RS [31, 25, 7] (LCC31) codes. The major algorithm improvement is that the interpolation is performed over a subset of test vectors to avoid redundant decoding. Also the factorization formula is reshaped to avoid large computation complexity overlooked in previous research. To maintain the effectiveness of algorithm improvements, we find it necessary to adopt the systematic message encoding, instead of the evaluation-map encoding used in the previous work on interpolation decoders. The LCC255 and LCC31 decoders are both implemented in 90nm CMOS process with the areas of 1.01mm 2 and 0.255mm 2 respectively. Simulations show that with 1.2V supply voltage they can achieve the energy efficiencies of 67pJ/bit and 34pJ/bit at the maximum throughputs of 2.5Gbps and 1.3Gbps respectively. The proposed algorithm changes, combined with optimized macroand micro-architectures, result in a 70% complexity reduction (measured with gate count). This new LCC design also achieves 17x better energy-efficiency than a standard Chase decoder (projected from the most recent reported Reed Solomon decoder implementation) for equivalent area, latency and throughput. The comparison of the two decoders links the significantly higher decoding energy cost to the better decoding performance. We quantitatively compute the cost of the decoding gain as the adjusted area of LCC255 being 7.5 times more than LCC31. Thesis Supervisor: Vladimir M. Stojanovid Title: Associate Professor