A High speed data link optimization for digitalized transfer to processing FPGA
A High speed data link optimization for digitalized transfer to processing FPGA
复制标题
用于数字化传输至处理 FPGA 的高速数据链路优化
DOI：
10.1051/epjconf/202125301006
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发表时间：
2021
影响因子：
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通讯作者：
A. Gadea
中科院分区：
文献类型：
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作者：
J. Collado;V. González;A. Gadea
需要数字处理的最先进的探测器阵列可能具有相当大数量的数字化信号链路。在几台实验核物理仪器中就是这种情况。此外，采样信号的数据速率(主要由各个检测器的信号带宽定义)可能不会耗尽单个FPGA收发机输入的能力。
预处理通常在收发器数据速率超过10Gbps的现代现场可编程门阵列中进行。此外，对于给定的FPGA处理能力，具有成本效益的FPGA具有有限数量的收发机。研究一种经济有效的方法来解决两种数据速率之间的不匹配，同时优化使用现场可编程门阵列资源，是当前工作的主题。
我们开发了一种基于时间域多路复用链路聚合的解决方案，采用夹层板的形式。该夹层将四个通道组合在一起，从高达2.5 Gbps的光纤或铜缆输入到高达10 Gbps的一个通道，并通过夹层连接器将它们提供给现场可编程门阵列。电路板本身是由一个小型的现场可编程门阵列通过双线接口(TWI)协议作为一个独立的智能设备来控制的，所以需要最小的速度控制。该解决方案还被开发用于容纳SOM模块和FMC连接器的主板，作为替代实施。基于JESD204通信协议，开发了相应的固件程序，实现了对现场可编程门阵列内部数据的解聚合和原始采样数据的恢复。该方法已经得到了验证，并且可以展望在Agata电子产品开发之外的应用。
State-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the data rate of the sampled signals, defined primary by the signal bandwidth of the individual detectors, may not exhaust the capabilities of a single FPGA transceiver input.
The preprocessing is usually carried out in a modern FPGA with transceiver data rate capabilities over 10Gbps. Moreover, cost effective FPGA have a limited number of transceivers for given FPGA processing capabilities. The investigation of a cost-effective and efficient solution to the mismatch between both data rates, optimizing simultaneously the use of the FPGA resources, is the topic of the present work.
We have developed a solution based on the Time Domain Multiplexing link aggregation, in the form of a Mezzanine board. This mezzanine combines four channels from an optical or copper input up to 2.5 Gbps to one up to 10Gbps, and serves them to the FPGA via the mezzanine connector. The board itself is controlled by a small FPGA by the Two Wire Interface (TWI) protocol as a standalone intelligent device, so minimum slow control is needed. The solution has been also developed for a motherboard housing a SoM module and FMC connector as an alternative implementation. An associated firmware has been developed to de-aggregate the data in the FPGA and recover the original sampled data, based on JESD204 communication protocol, inside the FPGA. The method has been validated and applications, beyond the development of the AGATA electronics, may be envisioned.