Ultrahigh Density Memristor Neural Crossbar for On-Chip Supervised Learning
Ultrahigh Density Memristor Neural Crossbar for On-Chip Supervised Learning
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DOI：
10.1109/tnano.2015.2448554
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发表时间：
2015-11-01
影响因子：
2.4
通讯作者：
Zhao, Weisheng
中科院分区：
文献类型：
--
作者：
Chabi, Djaafar;Wang, Zhaohao;Zhao, Weisheng
尽管未来计算系统有很多候选方案，但基于忆阻器的神经交叉开关 (NC) 因其低功耗、高密度和容错能力而被认为特别有前途。然而，它们的实现仍然受到 CMOS 神经元和学习细胞的限制的阻碍。在本文中，我们提出了一种基于忆阻器的 NC，它实现了片上监督学习。不是使用标准的 CMOS 神经元，而是使用简单的 CMOS 反相器来实现激活功能。更重要的是，我们提出了一种紧凑的学习单元，它由两个反向并行的二进制忆阻器的交叉锁存器组成。这种设计允许更高密度的集成，并且可以自然地扩展到多层神经网络。使用 CMOS 40 nm 设计套件和基于物理的高性能铁电隧道忆阻器紧凑模型，我们进行了瞬态仿真以验证所提出的神经交叉开关的功能。然后，我们通过级联单层网络构建多层NC；从而使网络能够学习非线性可分离函数（例如 XOR 函数）。最后通过蒙特卡罗模拟对容错性进行了评估。仿真结果分析表明我们提出的神经交叉开关在片上监督学习中的应用前景广阔。
Although there are many candidates for future computing systems, memristor-based neural crossbar (NC) is considered especially promising, thanks to their low power consumption, high density, and fault tolerance. However, their implementation is still hindered by the limitations of CMOS neuron and learning cells. In this paper, we present a memristor-based NC that implements on-chip supervised learning. Instead of using a standard CMOS neuron, a simple CMOS inverter realizes the activation function. More importantly, we propose a compact learning cell that consists of a crossbar latch of two antiparallel oriented binary memristors. This design allows for higher density integration and could be naturally extended to a multilayer neural network. Using the CMOS 40-nm design kit and a physics-based compact model of high-performance ferroelectric tunnel memristor, we performed transient simulations to validate the function of the proposed neural crossbar. Then, we construct a multilayer NC by cascading monolayer networks; thereby, enabling the network to learn non-linearly separable functions (e.g., XOR function). Finally, the fault tolerance is evaluated with Monte Carlo simulation. Analysis of simulation results demonstrates promising applications of our proposed neural crossbar for on-chip supervised learning.