ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
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DOI：
10.1109/hpca53966.2022.00060
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发表时间：
2021-07
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影响因子：
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通讯作者：
Hanchen Ye;Cong Hao;Jianyi Cheng;Hyunmin Jeong;Jack Huang;S. Neuendorffer;Deming Chen
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作者：
Hanchen Ye;Cong Hao;Jianyi Cheng;Hyunmin Jeong;Jack Huang;S. Neuendorffer;Deming Chen
高级综合（HLS）已被广泛采用，因为它显着提高了硬件设计的生产力，并使有效的设计空间探索（DSE）。现有的HLS工具是使用编译器基础设施构建的，主要基于单级抽象，如LLVM。然而，由于HLS设计通常具有内在的结构或功能层次，因此不同的HLS优化问题通常可以通过不同的抽象级别更好地解决。本文提出了ScaleHLS 1，一个新的可扩展和可定制的HLS框架，在一个多层次的编译器基础设施称为MLIR。ScaleHLS在多个表示级别上表示HLS设计，并提供了一个HLS专用的分析和转换库，以解决适当级别上的优化问题。使用这个库，我们提供了一个DSE引擎，自动生成优化的HLS设计。此外，我们还开发了一个HLS C前端和一个C/C++发射后端，用于将HLS设计转换为MLIR/从MLIR转换为端到端的编译流程。实验结果表明，与没有手动插入指令和代码重写的基线设计相比，仅通过Xilinx Vivado HLS进行优化，ScaleHLS以惊人的结果质量提高了性能-计算内核级程序的性能提高了768.1倍，神经网络模型的性能提高了3825.0倍。
High-level synthesis (HLS) has been widely adopted as it significantly improves the hardware design productivity and enables efficient design space exploration (DSE). Existing HLS tools are built using compiler infrastructures largely based on a single-level abstraction, such as LLVM. How-ever, as HLS designs typically come with intrinsic structural or functional hierarchies, different HLS optimization problems are often better solved with different levels of abstractions. This paper proposes ScaleHLS 1, a new scalable and customizable HLS framework, on top of a multi-level compiler infrastructure called MLIR. ScaleHLS represents HLS designs at multiple representation levels and provides an HLS-dedicated analysis and transform library to solve the optimization problems at the suitable levels. Using this library, we provide a DSE engine to generate optimized HLS designs automatically. In addition, we develop an HLS C front-end and a C/C++ emission back-end to translate HLS designs into/from MLIR for enabling an end-to-end compilation flow. Experimental results show that, comparing to the baseline designs without manual directives insertion and code-rewriting, that are only optimized by Xilinx Vivado HLS, ScaleHLS improves the performances with amazing quality-of-results – up to 768.1× better on computation kernel level programs and up to 3825.0× better on neural network models.