HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU
HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU
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DOI：
10.1109/dft56152.2022.9962336
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发表时间：
2022-10
期刊：
影响因子：
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通讯作者：
Pengzhou He;Yazheng Tu;A. Khalid;Máire O’Neill;Jiafeng Xie
中科院分区：
文献类型：
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作者：
Pengzhou He;Yazheng Tu;A. Khalid;Máire O’Neill;Jiafeng Xie
沿着大规模量子计算机的快速发展，后量子密码学（PQC）因其公钥密码系统易受量子攻击而受到研究界的广泛关注。与此同时，PQC领域最近的趋势逐渐转向硬件加速方面。根据这一趋势，这项工作提出了一种新的实现高性能多项式乘法硬件加速器NTRU（HPMA-NTRU）在不同的参数设置，基于格的PQC算法，目前正在考虑由美国国家标准与技术研究所（NIST）PQC标准化过程。总的来说，我们已经进行了三个层次的努力，以获得拟议的工作。首先，我们提出了一个新的教科书算法为基础的战略，以获得所需的多项式乘法算法NTRU。然后，我们已经映射的算法，建立一个高性能的多项式乘法硬件加速器，并已扩展到不同的参数设置适当的调整，该硬件加速器。最后，通过一系列的复杂度分析和基于实现的比较，我们已经表明，所提出的硬件加速器获得更好的面积-时间复杂度比国家的最先进的。这项工作的结果是重要的，将影响正在进行的NIST PQC标准化过程，并可以进一步部署，以构建高效的NTRU密码处理器。
Along the rapid development of large-scale quantum computers, post-quantum cryptography (PQC) has drawn significant attention from research community recently as it is proven that the existing public-key cryptosystems are vulnerable to the quantum attacks. Meanwhile, the recent trend in the PQC field has gradually switched to the hardware acceleration aspect. Following this trend, this work presents a novel implementation of a High-performance Polynomial Multiplication hardware Accelerator for NTRU (HPMA-NTRU) under different parameter settings, one of the lattice-based PQC algorithm that is currently under the consideration by the National Institute of Standards and Technology (NIST) PQC standardization process. In total, we have carried out three layers of efforts to obtain the proposed work. First of all, we have proposed a new schoolbook algorithm based strategy to derive the desired polynomial multiplication algorithm for NTRU. Then, we have mapped the algorithm to build a high-performance polynomial multiplication hardware accelerator and have extended this hardware accelerator to different parameter settings with proper adjustment. Finally, through a series of complexity analysis and implementation based comparison, we have shown that the proposed hardware accelerator obtains better area-time complexities than the state-of-the-art one. The outcome of this work is important and will impact the ongoing NIST PQC standardization process and can be deployed further to construct efficient NTRU cryptoprocessors.