A concept of analog-digital merged circuit architecture for future VLSI's
A concept of analog-digital merged circuit architecture for future VLSI's
复制标题
未来 VLSI 的模数合并电路架构的概念
DOI：
10.1007/bf00174243
复制
发表时间：
1996
影响因子：
1.4
通讯作者：
M. Nagata
中科院分区：
文献类型：
--
作者：
A. Iwata;M. Nagata
本文描述了一种利用脉冲调制信号的新型模数合并电路结构。通过重新考虑信息的表示和处理原理，以及遵循物理定律的电路操作，提出了新的电路体系结构，以克服现有VLSI技术的局限性。该结构利用了具有时间域模拟信息的脉宽调制(PWM)信号，并由新颖的脉宽调制电路构成，完成多输入算术运算、信号转换和数据存储。它具有开发深亚μm器件的高速开关能力的潜力，并将器件数量和功耗降低到二进制数字电路的十分之一。因此，它将有效地实现使用0.5-0.2μm刻度的CMOS器件的智能处理系统。
This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-μm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5–0.2 μm scaled CMOS devices.